Appendix A
10
2 1st 64K RAM chip or data line failure
2 timer test over.8254 CH
1 timer test to be complete. CMOS
checksum/battery check OK
k bits; Verify 8259 channel 2 masked interrupt by alternate
turning off and on the interrupt line. Setup Interrupt vectors.
(16)Battery power was lost.
(16)Keyboard controller gate A20 failure.
(16)BIOS ROM checksum.(Bee
3. Initialize 8259, reset
3 1st 64K RAM chip or data line failure
1 timer test over.8254 CH
0 timer test to be completed. Monochrome mode
(17)Test struck 8259’s interrupt bits
; Turn off interrupt then verify no interrupt mask
register is on. Setup video I/O operations.
(17)Initialize cache before memory auto
0 timer test over. About to start memory refresh. Color mode set.
(18)Testing Video memory.
(18)Test 8259 interrupt functionality; Force an interrupt and verify the interrupt
occurred. Test video memory
1 1st 64K RAM chip or data line failure
(18)Test base memory(first 128K)
(18)Shutdown during memory test.
(18)8254 timer initialization.(Beep)=1
1. Test 8259 interrupt controllers
1 1st 64K RAM chip or data line failure
(19)82 timer test over. Memory refresh test to be done next. About to look for
optional video ROM at segment C000 and give control to the optional video ROM
(19)Test 8259 functionality. Test stuck NON
Maskable Interrupt bits(Parity/I/O
check);Verify NMI can be cleared. 8259 Interrupt controller, channel 1 mask bits
(19)Clear and initialize base memory.
2 1st 64K RAM chip or data line failure
(1A)Memory refresh line is toggling. Going to check 15 micro second ON/OFF
time. Return from optional video ROM. Optional video ROM control OK
(1A)Display CPU clock.8259 Interr
upt controller, channel 2 mask bits test.
(1A)Initialize and test VDU adapters.
(1A)Copyright checksum errors.
(1A)8237 DMA controller initialization.(Beep)=1
(1B)Memory refresh period 30 micro second test complete. Base 64K memory test
about to start. Shadow RAM enable /disable completed. Display memory read/write
(1B)Test CMOS battery statu
(1b)Shutdown during memory sizing.
1 1st 64K RAM chip or data line failure
(1C)Display memory read/write test for main display type
program over. Display memory read/write test for alternate display OK.
(1C)Test CMOS RAM checksum. Test CMOS.
1 1st 64K RAM chip or data line failure
Programmable Interrupt Controller.(Beep)=1
(1D)Display memory read/write test for alternate display type complete if main
display memory read/write test returns error. Video retrace check OK.
(1D)Test DMA controller and page registers.
2 1st 64K RAM chip or data line failure
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